Methods and memory structures using tunnel-junction device as control element

ABSTRACT

A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation-in-part of co-pending andcommonly assigned application Ser. No. 10/116,497, filed Apr. 2, 2002,the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

[0002] This invention relates to integrated circuits including memorystructures and relates to methods for making such memory structures andto methods using such memory structures in electronic devices.

BACKGROUND

[0003] As computer and other electrical equipment prices continue todrop, the manufacturers of storage devices, such as memory devices andhard drives, are forced to lower the cost of their components. At thesame time, markets for computers, video games, televisions and otherelectrical devices are requiring increasingly larger amounts of memoryto store images, photographs, videos, movies, music, and other storageintensive data. Thus, besides reducing costs, manufacturers of storagedevices must also increase the storage density of their devices. Thistrend of increasing memory storage-density while reducing costs requiredto create the storage has been on-going for many years, and even opticalstorage media, such as CD-ROM, CD-R, CD-RIW, DVD, and DVD-R variants,are being challenged by device size limitations and costs. There isaccordingly a need for economical, high capacity memory structures andmethods for control of such memory structures. While resistive elements,transistors, and diodes have been used as control elements in the past,they have had various shortcomings in speed, silicon area requirements,and in allowing “sneak paths.”

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The features and advantages of the disclosure will readily beappreciated by persons skilled in the art from the following detaileddescription when read in conjunction with the drawings, wherein:

[0005]FIG. 1 is a schematic diagram of an embodiment of a cross-pointmemory array in which the disclosed memory cell structures can beutilized.

[0006]FIG. 2 is a schematic block diagram of an embodiment of a memorycell that includes a memory storage element and a control element forthe memory storage element.

[0007]FIG. 3 is a side-elevation cross-sectional view showingschematically an embodiment of a memory structure that includes a memorystorage element and a control element made in accordance with theinvention.

[0008]FIG. 4 is a top plan view of the embodiment of FIG. 3

[0009]FIG. 5 is a cross-sectional view that schematically depictsanother embodiment of a memory structure made in accordance with theinvention.

[0010]FIG. 6 is a cross-sectional view that schematically depictsanother view of the memory-structure embodiment of FIG. 5.

[0011]FIG. 7 is a schematic diagram illustrating use of a memorystructure made in accordance with the invention.

[0012]FIG. 8 is a graph showing resistance versus voltage for elementsof a memory structure made in accordance with the invention.

[0013]FIG. 9 is a circuit schematic illustrating use of a memorystructure made in accordance with the invention.

[0014]FIG. 10 is a circuit schematic illustrating an arrangement ofelements in memory structures made in accordance with the invention.

[0015]FIG. 11 is a circuit schematic illustrating an alternativearrangement of elements in memory structures made in accordance with theinvention.

[0016] FIGS. 12A-12C are graphs illustrating voltage versus timeprofiles of tunnel-junction devices made in accordance with theinvention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0017] Throughout this specification and the appended claims, the term“horizontal” means generally parallel to a substrate or generallyparallel to the layers of a multi-layer structure, and the term“vertical” means generally perpendicular to a substrate or generallyperpendicular to the layers of a multi-layer structure.

[0018] In accordance with the present invention, a method of using atunnel-junction device as a control element for a memory that has memorystorage elements that include an antifuse tunnel-junction device isdisclosed. This method includes selectively fusing the tunnel-junctiondevice of a memory storage element that includes such an antifusedevice. In a first embodiment of this method, a control elementincluding a second tunnel-junction device is connected in series withthe memory storage element, thereby forming a series combination. Whilethe second tunnel-junction device of the control element is protectedfrom fusing, a suitable current is applied to the series combination tofuse the first tunnel-junction device of the memory storage element.Other aspects of the invention include various memory structuresspecially adapted for the use of tunnel-junction devices as controlelements. Various memory structure embodiments are specially adapted foruse with the particular methods described below for usingtunnel-junction devices as control elements. These memory structures arealso described in detail below. Such methods and specially-adaptedmemory structures are used in memories for integrated circuits, storagedevices, and other electronic devices.

[0019]FIG. 1 is a simplified schematic diagram of an embodiment of across-point memory array 10 in which the disclosed memory cellstructures can be utilized. Memory arrangement 10 includes row selectionconductor lines R0, R1, R2 and column selection conductor lines C0, C1,C2. A memory cell 20 is connected between each row selection conductorline R0, R1, or R2 and each column selection conductor line C0, C1, orC2. It should be appreciated that the row selection conductor lines andthe column selection conductor lines are referred to by “row” and“column” terminology for convenience, and that in actual implementationsthe memory cells 20 do not necessarily have to be physically arranged inrows and columns. Each memory cell is uniquely accessed or selected by afirst selection line and a second selection line, each of which can beoriented in various ways. Also, the column lines do not have to beorthogonal to the row lines, but are illustrated in that manner for easeof understanding.

[0020]FIG. 2 is a simplified electrical block diagram of an embodimentof memory cell 20 which includes a memory storage element 23 that iselectrically connected to a control element 25 by an electrode E2.Memory storage element 23 and control element 25 are serially connectedbetween an electrode E1 and an electrode E3. Electrodes E1-E3 compriseconductive elements such as conductors, conductive regions, or otherconductive features, and it should be appreciated that electrode E2 cancomprise one or more electrically conductive elements.

[0021] Memory storage element 23 is configured as a change-of-statememory storage element, while control element 25 is configured as acontrol element for the change-of-state memory storage element andprovides current to memory storage element 23. More particularly, memorystorage element 23 is configured to predictably and reliably break downat a lower energy level than the control element, while thetunnel-junction region of control element 25 is configured for sustainedoperation as a control element for the memory.

[0022] Memory storage element 23 includes an effective cross-sectionalarea through which current flows, and, similarly, control element 25includes its own effective cross-sectional area through which currentflows. For example, such-an effective cross-sectional area can bedefined by the overlap of the interfaces between the element and theelectrodes on either side of the element. In the memory structuresdisclosed herein, control element 25 and memory element 23 can be of thesame device type, and control element 25 can have a cross-sectional areathat is about equal to or greater than the cross-sectional area ofmemory storage element 23. For example, the respective effectivecross-sectional areas may be made such that the memory storage elementwill break down at a lower energy level than the control element. Inother words, the ratio between the control element cross-sectional areaand the memory storage element cross-sectional area can be selected sothat the memory storage element functions as a state-change memorystorage element, while the control element has control elementcross-sectional area configured for sustained operation as a controlelement for the memory storage element. Thus, in accordance with thismethod, memory storage element 23 changes state at a lower energy levelthan the control element 25, which allows the memory storage element tobe programmed. In this manner, a memory cell is programmed byselectively providing sufficient energy to the cell to cause the memorystorage element to break down. A memory cell is read by providing alesser amount of energy to the cell and sensing whether current flowsthrough the cell. By way of illustrative example, in this method, theratio between the cross-sectional area of the control element and thecross-sectional area of the memory storage element can be in the rangeof about 2 to 20.

[0023] Other methods of ensuring that control element 25 sustainsoperation as a control element for memory storage element 23 aredescribed hereinbelow. In some of those methods, control element 25 canhave a cross-sectional area that is about equal to the cross-sectionalarea of memory storage element 23.

[0024] Memory storage element 23 can be an antifuse device, such as aprogrammable tunnel-junction device. The antifuse device can be either adielectric rupture type device or a tunnel-junction device. The tunneljunction can be formed from oxidized metal, thermally grown oxide, ordeposited oxides or nitrides. Memory storage element 23 may also beembodied with various device types and including various semiconductormaterials, such as polysilicon or polycrystalline silicon, amorphoussilicon, microcrystalline silicon, metal filament electro-migration,trap induced hysteresis, ferroelectric capacitor, Hall effect, orpolysilicon resistors. Other embodiments of memory storage element 23include tunneling magneto-resistive or capacitive elements as floatinggates. Still further, memory storage element 23 can be a read-onlyLeComber or silicide switch or a re-writable phase-change materialincluding a write-erase-write phase-change material. Memory storageelement 23 can also comprise a PIN diode or a Schottky diode.

[0025] In general, control element 25 can comprise a tunnel-junctiondevice or PN, PIN, or Schottky diodes. Other diodes that can be usedinclude Zener diodes, avalanche diodes, tunnel diodes, and a four layerdiode device such as a silicon controlled rectifier. Also, controlelement 25 can be a junction field-effect or bipolar transistor. Controlelement 25 is sized sufficiently to carry an adequate current such thatthe state of the storage element 23 can be changed. When the controlelement includes a diode, the diode can be formed using dopedpolysilicon, amorphous silicon, or microcrystalline silicon.

[0026] Memory storage element 23 and control element 25 can also be ofthe same device type, wherein both can comprise tunnel-junction devices,Schottky diodes, or PIN diodes, for example.

[0027] For conciseness, the disclosed memory structures are described asemploying tunnel-junction devices in both the memory storage elementsand control elements, and it should be appreciated that the memorystorage elements and control elements can be implemented as describedpreviously.

[0028] By way of illustrative examples, the disclosed memory structureswill be shown as integrated circuits that include an interlayerdielectric (ILD) that provides support and isolation between variousstructures of an integrated circuit. Such an interlayer dielectric maybe composed of insulating materials such as silicon dioxide, siliconnitride, or TEOS (tetraethylorthosilicate), for example. The interlayerdielectric can be deposited using several different technologies such aschemical vapor deposition (CVD), atmospheric pressure CVD, low pressureCVD, plasma enhanced CVD, physical vapor deposition (PVD), andsputtering. For convenience, regions and layers of such dielectric areidentified in the drawings by the reference designation ILD.

[0029]FIGS. 3 and 4 schematically depict an embodiment of a memory cellthat includes a memory storage element 23 disposed on a first conductor33. A control element 25 is disposed on a second conductor 35 that islaterally or transversely adjacent to first conductor 33. Memory storageelement 23 and control element 25 are thus horizontally, transversely,or laterally separated and each can have a generally horizontal planarextent. First and second conductors 33 and 35 can be substantiallycoplanar, and memory storage element 23 and control element 25 can alsobe substantially co-planar. A dielectric layer 41 is disposed over thefirst and second conductors 33 and 35 and includes openings 47 and 49over memory storage element 23 and control element 25. A conductivelayer 37 is disposed on dielectric layer 41 and extends into openings47and 49 so as to form an electrode between memory storage element 23and control element 25.

[0030] Memory storage element 23 can be formed of an oxide of firstconductor 33, while control element 25 can be formed of an oxide of theunderlying second conductor 35. Alternatively, memory storage element 23can be formed of an oxide that is different from an oxide of firstconductor 33, and control element 25 can be formed of an oxide that isdifferent from an oxide of second conductor 35. Memory storage element23 can also be a portion of an un-patterned oxide layer that can be adeposited oxide layer or a completely oxidized deposited metal layer,for example. Similarly, control element 25 can be a portion of anun-patterned oxide layer that can be a deposited oxide layer or acompletely oxidized deposited metal layer, for example.

[0031]FIGS. 5 and 6 schematically depict in cross-sectional views anembodiment of a memory structure that includes a plurality of memorycells each including a memory storage element 23 disposed between therim edge of a conductive well or tub 27 and a conductor 833 or 837 thatis vertically adjacent to the rim edge. Each memory cell furtherincludes a control element 25 disposed between the base of conductivetub 27 and a conductor 833 or 835 that is vertically adjacent to thebase. Memory storage element 23 and/or control element 25 can have ahorizontally planar extent and can be horizontally or verticallyseparated.

[0032] The memory cells of FIGS. 5 and 6 can be implemented in stackedlayers, for example, wherein a conductor 833 that is vertically adjacentto the rim edge of a given conductive tub 27 is vertically adjacent tothe base of a conductive tub 27 that is in an adjacent layer.

[0033] By way of illustrative example, conductor 833 can be a rowselection line while conductors 835 and 837 can be column selectionlines in a cross-point memory structure. Also by way of illustrativeexample, a conductive tub 27 can be laterally offset relative toconductor 833 that is vertically adjacent to the rim of such aconductive tub 27. Such a lateral offset may be used to control the areaof memory tunnel-junction oxide region 23, for example. As a result, aconductive tub 27 is laterally offset relative to another verticallyadjacent conductive tub 27 in an adjacent layer.

[0034] Memory storage element 23 can formed of an oxide of theconductive tub 27, and control element 25 can be formed of an oxide ofconductor 833 or 835 that is vertically adjacent to the base ofconductive tub 27. Alternatively, memory tunnel-junction oxide region 23can be formed of an oxide that is different from an oxide of the rim ofthe conductive tub 27, and control tunnel-junction oxide region 25 canbe formed of an oxide that is different from an oxide of conductor 833or 835. Memory storage element 23 can also be a portion of anun-patterned oxide layer that can be a deposited oxide layer or acompletely oxidized deposited metal layer, for example. Similarly,control element 25 can be a portion of an un-patterned oxide layer thatcan be a deposited oxide layer or a completely oxidized deposited metallayer, for example.

[0035] By way of illustrative example, FIG. 7 is a schematic diagramillustrating use of a memory structure embodiment made in accordancewith the invention in a memory. For clarity, different symbols are usedfor memory storage element 23 and control element 25 in FIGS. 7 and9-11, although their physical construction can be similar or evenidentical in some embodiments of the invention. Circuit ground isidentified by a conventional ground symbol with reference numeral 920 inFIGS. 7 and 9-11. As shown above in FIGS. 2-4, each memory cell 20comprises a memory storage element 23 electrically coupled with acontrol element 25. The memory cells 20 may be selectively addressedusing a row selection conductor line R0, R1, or R2 and a columnselection conductor line C0, C1, C2, or C3. Sense amplifiers 940 areelectrically coupled to the column selection lines C0, C1, C2, and C3 inFIG. 7. Similarly, sense amplifiers (not shown) may be electricallycoupled to row selection conductor lines R0, R1, and R2. To simplify thedrawing, column selection devices are shown only for column selectionline C3, but it will be readily recognized that each column selectionline may have such devices. An FET device 955 connects array nominalvoltage V_(a) from a supply pad 956 selectively to column line C3, forexample, when gated by a FET device 957 controlled by a write gatesignal WG applied from pad 958.

[0036]FIG. 8 is a graph showing a nonlinear resistance versus voltagecharacteristic curve for a tunnel-junction device of a type that can beused either as a storage-element antifuse or as a control element of amemory cell structure made in accordance with the invention. In FIG. 8,vertical axis 810 is the tunnel-junction resistance, R, shown on alogarithmic scale. Horizontal axis 820 is the applied voltage V_(a),also shown on a logarithmic scale. V_(fusing), the characteristicthreshold voltage at which the tunnel-junction device fuses (which canbe about 2 V±about 1 V, for example), is indicated along the voltageaxis. As shown by curve 830 in FIG. 8, the resistance R variesnonlinearly over a wide range when the applied voltage V is varied. Theresistance varies upward nonlinearly, typically by one to two orders ofmagnitude, from about 10⁵-10⁶ ohms at the fusing voltage, V_(fusing),shown at the right side of FIG. 8, to as high as 10⁸ ohms with a lowapplied voltage, e.g., about 10 millivolts (mV) as shown at the leftside of FIG. 8.

[0037] While the invention should not be construed as being limited tothe consequences of any particular theory of operation, the phenomenonillustrated by FIG. 8 is believed to contribute to functionality andperformance of some of the embodiments disclosed herein. In particular,the high resistance of a tunnel-junction device at low bias potentialsreduces any parasitic “sneak path” contribution of memory cells that arenot selected.

[0038]FIG. 9 is a circuit schematic illustrating use of a memorystructure made in accordance with the invention. Electrical energy isapplied from a current source 910 to memory cell 20 comprising theseries combination of a memory storage element 23 with a control element25. It will be recognized that the individual voltages across memorystorage element 23 and control element 25 will depend upon the commonseries current and the individual resistances of memory storage element23 and control element 25. In order to use the tunnel-junction device ofcontrol element 25 as a steering element, it may be made with resistancethat is low in comparison with the resistance of memory storage element23. By way of illustrative example, the tunnel-junction device may bemade with suitably low resistance by forming the tunnel-junction ofcontrol element 25 with a larger cross-sectional area than thecross-sectional area of memory storage element 23, as describedhereinabove. A suitable cross-sectional area ratio is about 2:1 or more,e.g., up to about 20:1. Thus, the cross-sectional area of controlelement 25 may advantageously be made at least twice the cross-sectionalarea of memory storage element 23. Cross-sectional area ratios evenhigher than 20:1 may be used, but require increased areas for thetunnel-junction devices of control elements 25, thus providing lowerdevice densities and incurring higher costs.

[0039]FIG. 10 is a circuit schematic illustrating, in a simplified case,an alternative memory structure embodiment using a referencetunnel-junction device. Reference tunnel-junction device 930 is similaror even identical in construction and effective cross-sectional area tocontrol element 25. Reference device 930 is connected in acurrent-mirror configuration with the series combination 20 of memorystorage element 23 and control element 25. Fusing voltage for memorystorage element 23 is applied to the series combination of memorystorage element 23 and control element 25 (shown at the left side ofFIG. 10) for a time interval. Sense amplifiers 940 and 950 operate toprevent a voltage greater than the fusing voltage for the controlelement from being present across control element 25 during or afterthat time interval. It should be noted that a sense amplifier such assense amplifiers 940 and 950 can sense voltage or current or both andcan sense them for one or more lines in a memory array. FIG. 11 is acircuit schematic illustrating an alternative arrangement of elements inmemory structures made in accordance with the invention. The circuitillustrated in FIG. 11 has a current source consisting of devices 940,950, 960, and 970. The particular type of current mirror sourceillustrated in FIG. 11 is commonly known as a cascode circuit. It willbe recognized by those skilled in the art that other types of currentsources may be used, such as Wilson current sources and “high-swing”cascode current sources.

[0040] FIGS. 12A-12C are graphs illustrating the electrical profile(voltage versus time) of the memory cell and tunnel-junction devicesmade in accordance with the invention. FIG. 12A (top graph) shows thevoltage across memory cell 20. FIG. 12B (middle graph) shows the voltageacross control element 25. FIG. 12C (bottom graph) shows the voltageacross memory storage element 23. A supply voltage V_(safe) is providedto the current source. At time t₀, the appropriate row and column areselected to begin a write operation to memory cell 20, i.e., by applyingwrite voltage across the memory cell. The first small bump indicated byreference numeral 975 on the voltage across control element 25 in FIG.12B is overshoot that occurs for a time determined by the current sourcecircuit response time. The falling edge indicated by reference numeral980 on the voltage curve of memory storage element 23 is the fusingevent, in which the antifuse is shorted. The second small bump indicatedby reference numeral 985 on the voltage across control element 25 inFIG. 12B corresponds directly in time to the fusing event 980, and itsmagnitude and duration are proportional to the response time of thecurrent source circuit. Finally, at time t_(f), the write pulse voltageis terminated to end the write operation.

[0041] The current source prevents a voltage greater thanV_(safe)-V_(source) from appearing across the control element 25 after afusing event. Thus, utilizing a current-source reference circuit, thecontrol element may be protected from fusing during a write operationthat fuses the antifuse of the memory storage element, even if thecontrol element and the memory storage element have identical effectivecross-sectional areas and device type or construction.

[0042] Thus, a method is performed in accordance with the presentinvention in which the tunnel junction of a control element may beprotected from fusing by coupling a sense amplifier to memory cell 20.At least one parameter is sensed: a suitable voltage and/or the currentthrough the series combination of memory storage element 23 and controlelement 25. The current through the series combination is controlled toa suitable value in accordance with the parameter sensed. In this methodembodiment, the suitable voltage sensed can be a voltage determined byelectrically coupling a reference tunnel-junction device to a currentsource.

INDUSTRIAL APPLICABILITY

[0043] The methods of the invention and memory structures speciallyadapted for those methods are useful in single-layer cross-point memoryarrays, multiple-layer cross-point memories, so-called “n+1” memorystructures, inter-pillar memory structures, and many other memorysystems. The use of tunnel-junction devices as control elements canresult in thinner, faster, and lower cost memory cells than those usingother control elements.

[0044] Although the foregoing has been a description and illustration ofspecific embodiments of the invention, various modifications and changesthereto can be made by persons skilled in the art without departing fromthe scope and spirit of the invention as defined by the followingclaims. For example, control of tunnel-junction device resistance ratiosmay be achieved by methods other than controlling cross-sectional areas,and various current source circuits may be employed other than thoseillustrated by the embodiments disclosed herein.

What is claimed is:
 1. A method of fusing a memory storage elementincluding a first tunnel-junction device, said method comprising thesteps of: connecting in series with said memory storage element acontrol element comprising a second tunnel-junction device, therebyforming a series combination, and applying a suitable current to saidseries combination, to fuse said first tunnel-junction device of saidmemory storage element, while protecting said second tunnel-junctiondevice of said control element from fusing.
 2. The method of claim 1,wherein said suitable current is a predetermined current sufficient forfusing said first tunnel-junction device of said memory storage element.3. The method of claim 1, wherein said suitable current is applied forat least a predetermined time interval.
 4. The method of claim 1,wherein said second tunnel-junction device has a characteristic fusingthreshold voltage, and said protecting step is performed by preventingvoltage across said second tunnel-junction device of said controlelement from exceeding said characteristic fusing threshold voltage. 5.The method of claim 4, wherein said fusing-threshold-voltage-preventingis performed by connecting a sense amplifier to said series combination,sensing at least one parameter of a suitable voltage and the currentthrough said series combination, and controlling said current throughsaid series combination to a suitable value in accordance with saidparameter sensed.
 6. The method of claim 5, wherein said suitablevoltage sensed is a voltage determined by electrically coupling areference tunnel-junction device to a current source.
 7. The method ofclaim 4, wherein said control element has a control-elementcross-sectional area, said memory storage element has amemory-storage-element cross-sectional area, and said control-elementcross-sectional area is made about equal to said memory-storage-elementcross-sectional area.
 8. The method of claim 4, wherein said controlelement has a control-element cross-sectional area, said memory storageelement has a memory-storage-element cross-sectional area, and saidfusing-threshold-voltage-preventing is performed by making saidcontrol-element cross-sectional area larger than saidmemory-storage-element cross-sectional area.
 9. The method of claim 8,wherein said control-element cross-sectional area is made at least twicesaid memory-storage-element cross-sectional area.
 10. The method ofclaim 4, further comprising the step of providing a referencetunnel-junction device, wherein said fusing-threshold-voltage-preventingis performed by connecting a sense amplifier to said series combination,sensing at least one parameter of a suitable voltage and the currentthrough said reference device, and controlling said current through saidseries combination to a suitable value in accordance with said parametersensed.
 11. The method of claim 10 wherein said reference device isconnected in a current-mirror configuration with said series combinationof said memory storage element and said control element.
 12. A method offusing a memory storage element including a first tunnel-junction devicehaving a first characteristic fusing threshold voltage connected inseries combination with a control element comprising a secondtunnel-junction device having a second characteristic fusing thresholdvoltage, said series combination being connected in parallel with areference element including a third tunnel-junction device having athird characteristic fusing threshold voltage less than or substantiallyequal to said second characteristic fusing threshold voltage, saidmethod comprising the steps of: applying a suitable current to saidseries combination, to fuse said first tunnel-junction device of saidmemory storage element while sensing at least one parameter of asuitable voltage and the current through said reference element; andcontrolling said suitable current applied through said seriescombination to a suitable value in accordance with said parametersensed, thus protecting said second tunnel-junction device of saidcontrol element from fusing, said protecting step being performed bypreventing voltage across said second tunnel-junction device of saidcontrol element from exceeding said second characteristic fusingthreshold voltage.
 13. A memory storage element made by the fusingmethod of claim
 1. 14. A memory cell including a memory storage elementmade by the fusing method of claim
 1. 15. A storage device including amultiplicity of memory storage elements made by the fusing method ofclaim
 1. 16. An electronic device including a multiplicity of memorystorage elements made by the fusing method of claim
 1. 17. A method ofprogramming a memory having a multiplicity of memory storage elements ofwhich each memory storage element includes a first tunnel-junctiondevice having a first characteristic fusing threshold voltage, saidmethod comprising the steps of: a) connecting in series with each ofsaid memory storage elements a control element comprising a secondtunnel-junction device having a second characteristic fusing thresholdvoltage, thereby forming a series combination; and b) selectively fusingsaid first tunnel-junction device of each selected memory storageelement by applying a suitable current to said series combination; whilec) preventing voltage across said second tunnel-junction device of saidcontrol element of each selected memory storage element from exceedingsaid second characteristic fusing threshold voltage, thus protectingsaid second tunnel-junction device of said control element of saidselected memory storage element from fusing; and d) repeating steps (b)and (c) for each selected memory storage element.
 18. A storage deviceincluding a memory made by the method of claim
 17. 19. An electronicdevice including a memory made by the method of claim
 17. 20. Anintegrated circuit including a memory made by the method of claim 17.21. The method of claim 17, wherein saidfusing-threshold-voltage-preventing is performed by connecting a senseamplifier to said series combination, sensing at least one parameter ofa suitable voltage and the current through said series combination, andcontrolling said suitable current in accordance with said parametersensed.
 22. The method of claim 17, further comprising the steps of:providing a reference element in parallel with said series combination,said reference element including a tunnel-junction device having a thirdcharacteristic fusing threshold voltage less than or substantially equalto said second characteristic fusing threshold voltage of said tunneljunction of said control element; and connecting a sense amplifier tosaid reference element, sensing at least one parameter of a suitablevoltage and the current through said reference element, and controllingsaid suitable current in accordance with said parameter sensed.
 23. Astorage device including a memory made by the method of claim
 22. 24. Anelectronic device including a memory made by the method of claim
 22. 25.An integrated circuit including a memory made by the method of claim 22.26. A memory structure comprising: a memory storage element, said memorystorage element having a memory storage element cross-sectional area; acontrol element comprising a tunnel-junction device, said controlelement having a control element cross-sectional area, said controlelement being electrically coupled to said memory storage element andbeing configured to control the state of said memory storage element;and a reference element, said reference element being configured as areference to protect said control element when selectively controllingthe state of said memory storage element.
 27. The memory structure ofclaim 26, wherein said control element cross-sectional area is largerthan said memory storage element cross-sectional area.
 28. The memorystructure of claim 26, wherein said memory storage element comprises atunnel-junction device.
 29. The memory structure of claim 26, furthercomprising first and second electrodes, wherein said control elementcomprises an oxide of said first electrode.
 30. The memory structure ofclaim 29, wherein said control element is disposed between said firstand second electrodes.
 31. The memory structure of claim 26, furthercomprising first and second electrodes, wherein said memory storageelement comprises an oxide of said second electrode.
 32. The memorystructure of claim 26, further comprising first and second electrodes,wherein said control element comprises an oxide of said first electrode,and wherein said memory storage element comprises an oxide of saidsecond electrode.
 33. The memory structure of claim 26, wherein saidmemory storage element comprises a tunnel-junction device portion, saidmemory structure further comprising first, second, and third electrodes,said memory storage element being disposed between said second and thirdelectrodes, wherein said control element comprises an oxide of saidfirst electrode, and wherein said memory storage element tunnel-junctiondevice portion comprises an oxide of said third electrode.
 34. Thememory structure of claim 26, wherein said control element and saidmemory storage element are substantially co-planar.
 35. The memorystructure of claim 26, wherein said control element and said memorystorage element are horizontally separated.
 36. The memory structure ofclaim 26, wherein said control element and said memory storage elementare vertically separated.
 37. An integrated circuit including the memorystructure of claim
 26. 38. A memory carrier including the memorystructure of claim
 26. 39. An electronic device configured to receivethe memory carrier of claim
 38. 40. An electronic device including thememory structure of claim
 26. 41. The memory structure of claim 26,further comprising a current source, said reference element including atunnel-junction device, said reference element being configured as areference for said control element in control of said current sourcewhen selectively controlling the state of said memory storage element.42. A memory structure comprising: a first electrode; a secondelectrode; a third electrode; a memory storage element disposed betweensaid second electrode and said third electrode, said memory storageelement having a memory storage element cross-sectional area; a controlelement disposed between said first electrode and said second electrode,said control element comprising a tunnel-junction device, said controlelement having a control element cross-sectional area, said controlelement being electrically coupled to said memory storage element andbeing configured to control said memory storage element; and a referenceelement, said reference element being configured as a reference toprotect said control element when selectively controlling the state ofsaid memory storage element.
 43. The memory structure of claim 42,wherein: said first electrode comprises a first conductor having a topsurface; said third electrode comprises a second conductor having a topsurface and being disposed horizontally adjacent to said firstconductor; said control element is disposed on said top surface of saidfirst conductor; and said memory storage element is disposed on said topsurface of said second conductor.
 44. The memory structure of claim 42,wherein said first conductor and said second conductor are substantiallyco-planar.
 45. The memory structure of claim 42, wherein said controlelement comprises an oxide of said first conductor.
 46. The memorystructure of claim 42, wherein said memory storage element comprises anoxide of said second conductor.
 47. The memory structure of claim 42,wherein said control element comprises an oxide of said first conductor,and wherein said memory storage element comprises an oxide of saidsecond conductor.
 48. The memory structure of claim 42, wherein saidcontrol element comprises an oxide different from an oxide of said firstconductor.
 49. The memory structure of claim 42, wherein said memorystorage element comprises an oxide different from an oxide of saidsecond conductor.
 50. The memory structure of claim 42, wherein: saidsecond electrode comprises a conductive tub having a base and a rim,said base and said rim being vertically separated; said first electrodecomprises a first memory selection conductor vertically adjacent to saidbase of said conductive tub; said control element is disposed betweensaid first memory selection conductor and said base of said conductivetub; said third electrode comprises a second memory selection conductorvertically adjacent to a portion of said rim of said conductive tub; andsaid memory storage element is disposed between said second memoryselection conductor and said rim of said conductive tub.
 51. The memorystructure of claim 42, wherein: said third electrode comprises atruncated conductive cone having a rim edge; said third electrodecomprises a conductor adjacent to said rim edge; and said memory storageelement is disposed between said rim edge and said conductor.
 52. Thememory structure of claim 42, wherein: said third electrode comprises aconductive pillar; said second electrode comprises a conductor laterallyadjacent to said conductive pillar; and said memory storage element isdisposed between said conductive pillar and said conductor.
 53. Thememory structure of claim 52, wherein said conductor comprises aconductive plate laterally adjacent to said conductive pillar.
 54. Thememory structure of claim 52, wherein said conductor comprises aconductive block laterally adjacent to said conductive pillar.
 55. Thememory structure of claim 42, wherein: said third electrode comprises aconductive tub; said second electrode comprises a conductor laterallyadjacent to said conductive tub; and said memory storage element isdisposed between said conductive tub and said conductor.
 56. The memorystructure of claim 55, wherein said conductor comprises a conductiveplate laterally adjacent to said conductive tub.
 57. The memorystructure of claim 55, wherein said conductor comprises a conductiveblock laterally adjacent to said conductive tub.
 58. The memorystructure of claim 42, wherein: said third electrode comprises aconductive structure having a vertical extent; said second electrodecomprises a non-horizontal conductive panel laterally adjacent to saidconductor, and comprises a horizontal conductive plate connected to saidconductive panel; said first electrode comprises a conductor laterallyadjacent to said conductive panel; said memory storage element isdisposed between an edge of said horizontal plate and said conductivestructure; and said control element is disposed between said conductorand said conductive panel.
 59. The memory structure of claim 58, whereinsaid conductive structure comprises a conductive pillar.
 60. The memorystructure of claim 58, wherein said conductive structure comprises aconductive tub.
 61. The memory structure of claim 58, wherein: saidconductor comprises an elongated conductive wall having a verticalextent; said conductive panel is laterally adjacent to said elongatedconductive wall; and said control element is disposed between saidconductive panel and said elongated conductive wall.
 62. The memorystructure of claim 42, further comprising a reference elementelectrically coupled to said third electrode to provide a currentreference for said control element.
 63. A memory structure comprising: aconductive structure having a vertical extent; a first memory storageelement and a first control element laterally adjacent to saidconductive structure; said first control element comprising atunnel-junction device, said control element having a cross-sectionalarea that is larger than a cross-sectional area of said first memorystorage element; a second memory storage element and a second controlelement laterally adjacent to said conductive structure; and said secondcontrol element comprising a tunnel-junction device and said secondcontrol element having a cross-sectional area that is larger than across-sectional area of said second memory storage element.
 64. Thememory structure of claim 63, further comprising: further conductivestructure having a vertical extent vertically adjacent to saidconductive pillar; a third memory storage element and a third controlelement laterally adjacent to said further conductive structure; saidthird control element comprising a tunnel-junction device, said thirdcontrol element having a cross-sectional area that is larger than across-sectional area of said third memory storage element; a fourthmemory storage element and a fourth control element laterally adjacentto said further conductive structure; and said fourth control elementcomprising a tunnel-junction device, said fourth control element havinga cross-sectional area that is larger than a cross-sectional area ofsaid fourth memory storage element.
 65. A memory structure comprising:means for storing a memory state; means for controlling said means forstoring; said means for controlling including a tunnel-junction device,and said means for controlling having a larger cross-sectional area thansaid means for storing.
 66. The memory structure of claim 65, whereinsaid means for controlling further comprises reference means and meansfor controlling current responsive to said reference means.
 67. A memorystructure comprising: a plurality of layers of memory cells; each memorycell comprising a first electrode, a second electrode, a thirdelectrode, a memory storage element disposed between said secondelectrode and said third electrode, and a control element disposedbetween said first electrode and said second electrode; and said controlelement including a tunnel-junction device and having a cross-sectionalarea that is greater than a cross-sectional area of said memory storageelement.
 68. The memory structure of claim 67 wherein: said secondelectrode comprises a conductive tub having a base and a rim that arevertically separated; said first electrode comprises a first memoryselection conductor vertically adjacent to said base of said conductivetub; said control element is disposed between said first memoryselection conductor and said base of said conductive tub; said thirdelectrode comprises a second memory selection conductor verticallyadjacent to a portion of said rim of said conductive tub; and saidmemory storage element is disposed between said second memory selectionconductor and said rim of said conductive tub.
 69. The memory structureof claim 67 wherein: said third electrode comprises a conductive pillar;said second electrode comprises a conductor laterally adjacent to saidconductive pillar; and said memory storage element is disposed betweensaid conductive pillar and said conductor.
 70. The memory structure ofclaim 67 wherein: said third electrode comprises a conductive tub; saidsecond electrode comprises a conductor laterally adjacent to saidconductive tub; and said memory storage element is disposed between saidconductive tub and said conductor.
 71. A memory structure comprising: aplurality of layers of memory cells; each memory cell comprising meansfor storing a memory state and means for controlling said means forstoring; and said means for controlling including tunnel-junction devicemeans and having a larger cross-sectional area than said means forstoring.
 72. The memory structure of claim 71, further comprisingreference means for providing a current reference for said means forcontrolling said means for storing.
 73. A method of making a memorystructure, said method comprising the steps of: a) forming a controlelement of a device type including a tunnel-junction device; b) forminga memory storage element having a cross-sectional area that is smallerthan a cross-sectional area of said control element; c) electricallycoupling said control element with said memory storage element; d)providing first conductive connections to said memory storage element;and e) providing second conductive connections to said control element,said second conductive connections being adapted to control said controlelement for controlling said memory storage element.
 74. A memorystructure made in accordance with the method of claim
 73. 75. A methodof making a memory structure, said method comprising the steps of:creating a first electrode; forming on the first electrode a controlelement of a device type including a tunnel-junction device; creating asecond electrode; and forming a memory storage element having across-sectional area that is smaller than a cross-sectional area of saidcontrol element.
 76. The method of claim 75, wherein forming the controlelement on the first electrode comprises forming an oxide different froman oxide of the first electrode.
 77. The method of claim 75, whereinforming the memory storage element on the second electrode comprisesforming an oxide different from an oxide of the second electrode. 78.The method of claim 75, wherein forming the memory storage elementcomprises forming the memory storage element on a top surface of thefirst electrode.
 79. The method of claim 75, wherein forming the controlelement comprises forming the control element on a top surface of thesecond electrode.
 80. The method of claim 75, wherein: forming thememory storage element comprises forming the memory storage element on atop surface of the first electrode; forming the control elementcomprises forming the control element on a top surface of the secondelectrode.
 81. The method of claim 75, wherein forming the controlelement comprises forming the control element on a side surface of thefirst electrode; creating a second electrode comprises creating a secondelectrode that is in contact with the control element and laterallyadjacent to the first electrode; and forming the memory storage elementcomprises forming the memory storage element on a side surface of thesecond electrode.
 82. The method of claim 75 further including forming aconductive structure having vertical extent in contact with the memorystorage element and laterally adjacent to the second electrode.
 83. Themethod of claim 75 wherein: forming the control element comprisesforming the control element on a horizontal surface of the firstelectrode; creating a second electrode comprises forming a conductivetub vertically adjacent to the first electrode, said conductive tubhaving a base in contact with the control element and said conductivetub having a rim vertically separated from the base; and forming thememory storage element comprises forming the memory storage element onthe rim of the conductive tub.
 84. A memory structure made in accordancewith the method of claim
 75. 85. A method of making a memory structure,said method comprising: forming in a first memory layer a plurality ofmemory cells, each memory cell including a memory storage element and acontrol element including a tunnel-junction device and said controlelement having a cross-sectional area that is larger than across-sectional area of the memory storage element; and forming in asecond memory layer a plurality of memory cells, each memory cellincluding a memory storage element and a control element including atunnel-junction device and said control element having a cross-sectionalarea that is larger than a cross-sectional area of the memory storageelement.
 86. The method of claim 85, wherein forming in a first memorylayer a plurality of memory cells comprises forming in the first memorylayer a plurality of memory tunnel-junction oxide regions and aplurality of control tunnel-junction oxide regions.
 87. The method ofclaim 85, further comprising forming a plurality of reference elements,a reference element being formed corresponding to each control elementformed.
 88. The method of claim 87, wherein forming a plurality ofreference elements comprises forming a plurality of referencetunnel-junction oxide regions.
 89. A memory structure made by the methodof claim
 85. 90. A storage device including a memory structure made bythe method of claim
 85. 91. An electronic device including a memorystructure made by the method of claim
 85. 92. An integrated circuitincluding a memory structure made by the method of claim 85.